How to reduce PCB Design errors and increase efficiency

PCB circuit board design is a critical and time-consuming task, and any problems require engineers to check the entire design network by network and component by component. It can be said that circuit board design requires as much care as chip design. today qihe smt machine will discuss you with how to design PCB to reduce errors and improve efficiency?

A typical board design flow consists of the following steps:

The first three stages take maximum time because the schematic review is a manual activity. Imagine a SoC board with 1000 or more connections. Reviewing each and every connection manually is a tedious task. It is almost impossible to check each, and this leads to problems in the final board, like wrong connections, floating nodes, etc.

The schematic capture phase generally faces the following types of problems:

Underscore errors: such as APLLVDD and APLL_VDD

● Capitalization issues: such as VDDE and vdde

● typos

● Signal short circuit problem

● …and many more

In order to avoid these mistakes, PCB design should have a way to check the entire schematic in a few seconds. This approach can be implemented using schematic simulation, which is rarely seen in current board design flows. Schematic simulation allows viewing of the final output at the required nodes, so it automatically checks for any connection problems.

The following is explained through a project example. Consider a typical block diagram of a circuit board:

In a complex board design, the number of connections may reach thousands, and a very small number of changes is likely to waste many hours of checking.
Schematic simulation not only saves design time, but also improves board quality and increases the efficiency of the entire process.

A typical device under test (DUT) has some of the following signals:

The device under test will have a variety of signals after some pre-conditioning, and there are various modules, such as voltage regulators, op amps, etc., for signal conditioning. Consider an example supply signal obtained through a voltage regulator.

To verify connection relationships and perform overall checks, schematic simulation is used. Schematic simulation consists of schematic creation, testbench creation, and simulation.

During testbench creation, stimulus signals are fed to the necessary inputs and outputs are observed at signal points of interest.

The above process can be realized by connecting the probe to the node to be observed. Node voltages and waveforms can indicate whether the schematic has errors. All signal connections are checked automatically.

Let’s take a look at a fragment of the image above, where the probed nodes and voltages are clearly visible:

So with the help of simulation, we can directly observe the results and confirm that the board schematic is correct. In addition, investigation of design changes is enabled by careful adjustment of stimulus signals or component values. Schematic simulation can thus save board design and inspection personnel a lot of time and increase the chances of correct design.

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